Design of A 0.1 - 40 GHz Distributed Broadband Power Amplifier

A 0.1 - 40 GHz distributed broadband power amplifier chip based on a 0.15 um GaAs pHEMT process was designed and fabricated. A distributed structure was used to increase bandwidth. A 9-stage cascode topology was used to increase the gain of the circuit. The circuit layout was designed with a full-wave electromagnetic simulation technology, thus the electromagnetic interference inside the chip was decreased effectively．The PA chip was tested on wafer at continuous wave mode with drain bias 7 V and drain current 200 mA. The test results show that, at the frequency range of 0.1 GHz to 40 GHz, the small-signal gain of the balanced PA is higher than 15 dB and the gain flatness is lower than ±1 dB. Both the input and output return losses are below -12 dB. The 1 dB compression output power of the PA is higher than 18 dBm.