Investigation of Timing Parameters in Single-Flux-Quantum Circuits Using Low Critical-Current Junctions and Low Bias Voltages

In this study, the trade-off among power consumptions, operating frequencies, and error rates in low-power single-flux-quantum (SFQ) circuit is investigated. The power consumption of SFQ circuits can be reduced by the lowering critical currents ($I_{\mathrm{c}}$ values) of the Josephson junctions (JJs), or the bias voltage ($V_{\mathrm{b}}$). The shifts and spreads of timing parameter fluctuations when $I_{\mathrm{c}}$ and $V_{\mathrm{b}}$ were lowered were numerically analyzed, with consideration of thermal noise at 4.2 K. The timing behaviors after $I_{\mathrm{c}}$ was lowered were relatively simple, being based on the signal-to-noise ratio, whereas those for lowered $V_{\mathrm{b}}$ values were complicated because of the dynamic behaviors of JJs driven at reduced voltage. The simulation results imply that the operating frequencies decreased because the timing windows narrowed, but the highest energy efficiency was obtained when we lowered $I_{\mathrm{c}}$ or $V_{\mathrm{b}}$ to 6.25% of their conventional values, and the energy reduction after lowering of $V_{\mathrm{b}}$ was 26% better than that after lowering of $I_{\mathrm{c}}$. Moreover, if a small error rate (for example $10^{-6}$) is acceptable, further improvement in energy efficiency would be expected at significantly higher clock frequencies than would be the case if the SFQ circuit must exhibit error-free operation.