On development of 600-850 V 6H-SiC LDMOS transistors using silane-ambient implant anneal

In this work, we report on development of 600-850 V SiC LDMOSFET's, which for the first time utilize silane-overpressure implant annealing, in comparison to earlier works. A 2-D model using Medici/sup TM/ software from Avant! Corporation was used to optimize the structure, and a modified implant anneal with silane overpressure was used to improve the surface morphology of implanted regions. Further, drain and gate electrode extensions were used to increase the blocking voltage.