A Modified Inter-Stage Binary Comparator Based on Parallel Prefix for Low Power and High-Density Applications

A recently reported parallel prefix tree approach is used to realize the N-bit comparator. The sub-circuit is modified to achieve the same functionality for a comparator with a lesser number of transistors, power and power delay product. To achieve maximum swing at the output, a modification technique is introduced to overcome the effect of weak zero. An extra path is provided between the output and ground to overcome the effect of poor noise margin in the circuit. The implemented circuit is based on the pass transistor logic. The pre-layout simulation of the design is performed using the Cadence EDA tool of 180 nm standard CMOS technology. The proposed XNOR-AND cell element of comparator shows improvement in the number of transistors, area, and average power.