Partitioning RSFQ Circuits for Current Recycling

RSFQ circuits require a DC bias current to operate properly. The bias current in conventional RSFQ circuits is supplied to each gate, resulting in large current requirements in VLSI complexity SFQ systems, on the order of tens to hundreds of amperes. These high currents are difficult to supply and distribute. Superconductive input/output pins and bias lines support this limited current. Large currents however require significant metal and input pin resources. In addition, large currents can inductively couple to sensitive superconductive inductors, degrading circuit operation and producing errors. Current recycling is a well known technique to reduce these bias currents. RSFQ circuits with similar bias current requirements can be placed on separate ground planes and serially biased. The inputs and outputs of these circuits are galvanically decoupled and require drivers and receivers between connections. In this paper, a methodology for automated partitioning of complex RSFQ circuits into blocks with similar bias currents is described, where the number of connections among the blocks is minimized. Blocks with a significant difference in bias current are balanced using dummy padding structures. These blocks are biased in series, reducing the total bias current by the number of partitions. The Fiduccia-Mattheyses algorithm is modified with RSFQ specific enhancements to partition the system. A geometric partitioning approach, optimized by simulated annealing, is also proposed. These algorithms are integrated into the circuit placement process, and the methodology is evaluated using several modified ISCAS’89 sequential benchmark circuits and the AMD2901. The proposed partitioning methodology is intended for use within an automated EDA flow to enable current recycling for arbitrary (non-uniform, irregular) VLSI complexity RSFQ circuits, drastically reducing overall bias current and input requirements