FPGA-Based Implementation of MSPWM Utilizing 6-Input LUT for Reference Signal Generation

Field Programmable Gate Arrays (FPGAs) have become dominant tools for implementing different types of Pulse Width Modulation (PWM) due to the flexibility they provide compared to other DSPs. Different PWM types have been implemented such as Sinusoidal PWM (SPWM), Space Vector (SVPWM), carrier phase shifted SPWM (CPS-SPWM) using different FPGA boards. In this paper, we designed and implemented a new circuit of a Modified Sinusoidal PWM (MSPWM) on FPGA. The circuit was described in VHDL and implemented on ZYNQ-7000 FPGA board. Before the implementation, the design was simulated using MATLAB Simulink where the MSPWM was used to control a single-phase DC to AC inverter to study the performance in terms of Total Harmonics Distortion (THD) reduction compared to SPWM. Two reference sinusoidal signals with 180-degree phase shift were generated using 8-bit accumulator and 64 values Look Up Table (LUT) based on Direct Digital Synthesizer (DDS) technique. They were compared with triangular carrier signal which has a one-third zero values at a specific interval of its period to produce four PWM signals. The resource utilization table indicates that only 9% of the LUT, 0.2% of the FF (flip flop), and 6.25% of the buffers have been used for implementing the MSPWM.