Verification of Interconnect RTL Code for Memory-Centric Computing using UVM

This document is about the verification of an interconnect (i.e. switch) RTL code that is based on Gen-Z protocol using Universal Verification Methodology (UVM). Ports in the switch for transmission packets are connected to virtual interfaces with UVM. The packets that are generated in the UVM environment are transmitted into the ports of the switch through the virtual interfaces. For verifying the switch logic, we designed sequence items and a virtual sequencer and simulated it.