Optimized programming of multilevel flash EEPROMs

The trade-off between speed and dispersion of programmed threshold voltages is investigated in 0.25 /spl mu/m flash memory technology. It is shown that ramped gate programming provides tighter distributions of programmed threshold voltages than its conventional Box-Waveform counterpart, allowing one to write a larger number of b/s. In particular at low programming speed ramped gate programming is shown to allow four level schemes without program and verify operations, with a program bandwidth potentially approaching 30 Mb/s in the conventional 1-b-per-cell scheme (and correspondingly higher values in the multilevel case). Instead, sixteen level schemes without program and verify do not seem practically feasible.