Tunnel FET Negative-Differential-Resistance Based 1T1C Refresh-Free-DRAM, 2T1C SRAM and 3T1C CAM

A refresh free and scalable ultimate DRAM (uDRAM) with 1T1C bitcell is introduced in this paper. The memory uses the Negative Differential Resistance (NDR) property of Tunnel Field Effect Transistors (TFET) and storage capacitor leakage to retain data statically. The static data retention eliminates the need for refresh. The uDRAM allows more than 5x scaling of a storage capacitor in comparison to Dual-Data-Rate (DDR) and embedded DRAMs. This concept is further extended to design a 2T1C ultimate SRAM (uSRAM) and 3T1C ultimate CAM (uCAM). Area of 0.0275 μm
²
, 0.07 μm
²
and 0.104 μm
²
are achieved for DRAM, SRAM and CAM bitcells, respectively, when implemented in TFET-compatible 28 nm FDSOI-CMOS process. The uDRAM achieves an estimated throughput gain up-to 9.94% in comparison with a CMOS DRAM, owing to refresh removal in the DDR configuration. The 2T1C SRAM with read and write cycle times of sub-2ns and sub-4ns are demonstrated. The results show ultra-low leakage of less than 1 fA/bit for the proposed designs.