An Intelligent Algorithm for Mapping of Applications on Parallel Reconfigurable Systems

An increasing demand for computational power in daily used applications has led to implementation of different computing platforms. Among them, reconfigurable platforms which are based on FPGAs, have been widely used in recent years. While they are flexible, the communication cost between different computational tasks implemented in different locations of FPGA is one of the main challenges when it comes to improving the performance. In this paper, mapping of application tasks into processing platforms is studied. We presented a new method based on neural networks. Firstly, using Node2vec embedding algorithm, dimensions reduction, and rotation and scale, an initial mapping of task interaction graph nodes into processing structure FPGAs was obtained. Secondly, the dilation and maximum capacity utilization optimization were done using the stochastic gradient descent (SGD) method and loss functions. After performing experiments and comparing the proposed method with a similar method, results showed that the proposed method was superior in performance in terms of dilation (11.28%) and showed a poorer performance in terms of maximum capacity utilization (4.30%).