FPGA Acceleration Architecture Design and Implementation of LTE Physical Downlink Shared Channel

Using FPGA to realize the bit-level data processing of LTE physical downlink shared channel (PDSCH), and using it as the core device of data processing, can effectively improve the performance of data processing of the system, which can apply to the large-capacity real-time signal and protocol processing of the satellite mobile communication virtualization station based on LTE. This work presents a new hardware acceleration architecture based on combining the standard processing platform and the FPGA. The bit-level part with large data processing capacity is realized in FPGA, and the functions of the superior network layer, including the MAC layer are realized on CPU. Datastream through modules includes data processing, transmission block CRC24A attachment, parameter calculation of code block segmentation, code block CRC24B attachment and then parallel-serial conversion, Turbo coding, code block interleaving, bit selection, and collection, finally through the code block cascade to output to finish the PDSCH bit-level data processing.