Fast Fractional Motion Estimation Hardware Design of Inter Predication for AVS2

Fractional Motion Estimation (FME) is a very significant part of video coding technology, but its high computational complexity often limits the real-time performance and makes the area cost very high in hardware design. In this brief, this paper puts forward some novel joint optimizations with taking both algorithm and architecture into account to increase the throughput and reduce the area cost as much as possible, including SATD-based inter coding unit (CU) early split method and pipeline the 25 points parallel search and interpolation. In addition, to further improve throughput, for CUs with size greater than 8×8, we adopt the method of splicing to further reduce redundant operations and improve the ability of architecture reuse. These ideas help us save nearly 75% of the computational effort and complexity in FME of inter frame prediction. Finally, verified by the Xilinx Vivado HLS, the experiment results show that the algorithms and architecture proposed in this paper are able to process videos of 1920×1080@60 fps under the 300 MHz clock frequency with 3% bitrates increase in average.