A 17.7-pJ/Cycle ECG Processor for Arrhythmia Detection with High Immunity to Power Line Interference and Baseline Drift

A full-customized electrocardiograph (ECG) processor for arrhythmia detection is proposed in this paper, which is composed of detection engine, circulated buffer, register bank and instruction/data interfaces. The processor, which is fed by 0.9-V parallel digitized ECG signals, generates stamp pulses of detected QRS-complexes and arrhythmia location by searching for local extremes of signal derivative with self-adaptive thresholds. The precision (Pre) and sensitivity (Sen) of the proposed algorithm are 99.1% and 96.9% respectively. The extra false positive (FP) rate of proposed ASIC-implemented ECG processor is extremely low even with power-line interference (PLI) of 0.0663 Vp and/or rail-to-rail baseline drift (R2R BLD). The processor stands out for its relatively low power consumption of 17.7 pJ/cycle with superior robustness to interferences compared to other designs in literature.