A Sub-1-mW Fractional-N Phase-Locked Loop For Mixer-Based Wake-up Receiver In Wireless Sensors

This paper presents a 750 μW fractional-N Phase-Locked Loop (PLL) for Wake-up Receiver (WuR) architecture. The frequency synthesizer operates from 1.5 to 2.3 GHz and the proposed quadrature phase generator provides four local oscillator signals with the frequencies of 263 MHz, 433 MHz, 868 MHz, and 920 MHz. Several techniques are adopted to facilitate ultra-low-power operation. Inside the Voltage-Controlled Oscillator (VCO), the inductance for the resonance is maximized to provide low power consumption and the capacitor banks are optimized to cover the whole frequency range considering process, voltage, and temperature variations. Controllable tail transistors adjust the current consumption of the VCO and prevent swing reduction due to the large equivalent capacitance of the capacitor banks at the lower frequencies. Furthermore, the power consumption of the digital parts is reduced by operating with a lower supply voltage generated by an on-chip voltage regulator. The PLL is implemented using a 60 nm CMOS process with a core size of 0.5 mm × 0.7 mm. The whole PLL consumes 750 μW and the VCO offers the phase-noise performance of -93.9 and -116.1 dBc/Hz at 100 kHz and 1 MHz offset frequencies from the carrier frequency of 1.85 GHz.