A circuit-algorithm codesign method to reduce the accuracy drop of RRAM based computing-in-memory chip

Deep neural networks have exhibited superior performance in many areas such as image classification and so on. Due to the “memory bottleneck the energy efficiency of traditional chips is limited. The RRAM based computing-in-memory chip offers a new computing paradigm to remove data transfer between computing units and memory units. However, the nonidealities of RRAM device and analog circuits will reduce the on-chip accuracy. Here, we propose a novel codesign method to reduce the accuracy drop in the post-mapping phase of computing-in-memory system. First, we introduce the architecture of computing-in-memory chip and develop the compact model of the device and peripheral circuits. To reduce the accuracy drop, we present a novel codesign method by add nonidealities of device and circuits in the training phase of neural network. Finally, we found the post-mapping accuracy could recover more than 20% accuracy after device and circuit aware training.