A CMOS 60-GHz Asymmetrical SPDT Switch with Enhanced Power Handling Capability

In this work, a novel single-pole double-throw (SPDT) switch with high power handling capability along with a good isolation is presented. To achieve both excellent 1-dB compression point (P1dB) and isolation simultaneously, an asymmetrical SPDT structure is used. By carefully layout the design, this SPDT switch achieves a simulated P0.5 dB of 26 dBm, a minimum insertion loss of 1.7 dB and an isolation of 40 dB at 60 GHz in transmitter mode; a minimum insertion loss of 1.8 dB and isolation of 25 dB at 60 GHz in receiver mode. The circuit is designed in 0.13-μm CMOS process. The area of this design, excluding pads, is 1010 μm × 186 μm.