Data Flow Mapping onto DNN Accelerator Considering Hardware Cost

Deep Neural Networks (DNNs) has created outstanding results in computer vision and image processing recently. Computational Algorithms complexity has led to widespread research in this field. Besides, using a DNN accelerator is an effective method in order to hasten the computation in those algorithms. The majority of DNN accelerator use parallelism Processing Elements (PEs) in order to lessen hardware costs. Regarding high volume of input data in image processing, lessening computing runtime is considered as an open challenge in DNNs accelerator. All above-mentioned issues have created different data flow mapping method in DNNs accelerator. This paper presents the new data flow mapping on Resnet34, regarding stationaries concepts; moreover, evaluates computing runtime in each step of mapping. We also propose a new data flow mapping method based on weight stationary in Resnet34, which reduces computing runtime, by 50.6%.