Design of an Enhanced Reconfigurable Chaotic Oscillator using G4FET-NDR Based Discrete Map

In this paper, a novel chaotic map is introduced using a voltage controlled negative differential resistance (NDR) circuit composed of an n-channel and a p-channel silicon-on-insulator (SOI) four-gate transistor (G
⁴
FET). The multiple gates of the G
⁴
FET are leveraged to create a discrete chaotic map with three bifurcation parameters. The three tunable parameters are the gain of a transimpedance amplifier (TIA), top-gate voltage of n- channel G
⁴
FET, and top-gate voltage of p-channel G
⁴
FET. Two methods are proposed for building chaotic oscillators using this discrete map. The effect of altering bifurcation parameters on chaotic operation is illustrated using bifurcation diagrams and Lyapunov exponent. A design methodology for building flexible and reconfigurable logic gate is outlined and the consequent enhancement in functionality space caused by the existence of three independent bifurcation parameters is demonstrated and compared with previous work.