Low Power Implementation of ECG R-wave Peak Detector in 180 nm CMOS Process

With the widespread use of sensor technology, monitoring heart conditions is feasible and widely accessible. Electrocardiogram (ECG) signals contain rich information concerning several heart diseases including sudden cardiac arrests (SCAs). Continuous monitoring of heartbeat using wearable devices can help detect heart irregularities. While current wearable devices transmit raw ECG signals for processing, this paper proposes a novel on-chip ECG feature extraction system implemented on standard 180 nm CMOS technology using the Cadence Virtuoso tool. The proposed design detects all peaks with a high degree of sensitivity compared to earlier systems. Future enhancements of the design will include the determination of the R to R interval. The total power consumption for the design is just 0.379 nW, which is much lower in comparison to other implementations. This design has been verified on ECG data acquired from live subjects in a lab environment. In addition, the design is also verified on Physionet, an archive of well-characterized ECG databases collected from healthy subjects while exercising. Two datasets are tested into this design to check for peak detection and heart rate abnormality.