A 9pW/bit 400mV 3T Gain-Cell eDRAM for ULP Applications in 28 nm FD-SOI

The silicon area and power consumption of ultra-low power (ULP) applications is often dominated by embedded memories [1] , [2] . A popular approach for power reduction is scaling the supply voltage ( V DD ) down to the sub-threshold (sub- V T ) region, however, the conventional 6-transistor (6T) SRAM bitcell becomes unreliable at scaled voltages [3] , [4] .