Potential Well Based FDSOI MOSFET: A Novel Planar Device for 10 nm Gate Length

A novel planar device having potential wells (PW) in the source and drain regions of MOSFET is reported. The device was realized by introducing wells in the BOX under source/drain regions of FDSOI MOSFET and is called PWFDSOI MOSFET. The simulations confirmed that the potential wells played key role in reducing the OFF current of the device by orders of magnitude in a scaled device having gate length of 10 nm while reducing the ON current marginally thus improving the ON-to-OFF current ratio (I
_ON
/I
_OFF
) of the device. An I
_ON
/I
_OFF
ratio of ~7 × 10
⁵
was realized in a 10 nm gate length (6 nm node) PWFDSOI MOSFET having subthreshold swing (SS) of 87 mV/decade. The study was done on devices with unstrained silicon channel.