Edge Inference with NEM Relays

Energy efficient implementation of machine learning applications is crucial for attaining cognition at the edge. State of the art systems with Deep Neural Networks (DNN) are memory and computationally intensive impeding its deployment on resource-constrained embedded systems. Building on a hardware-software codesign paradigm for dedicated accelerators with algorithm, architecture and novel device integration allows for an optimized design framework. In this work, we leverage the inherent sparsity feature of neural networks and static nature of the weight memory in the inference mode, to introduce NEMs-based neural accelerator engine. The design achieves 6x better energy efficiency and 3x lower area than conventional CMOS designs.