Dynamic binary translation and optimization | IEEE Journals & Magazine | IEEE Xplore

Dynamic binary translation and optimization


Abstract:

We describe a VLIW architecture designed specifically as a target for dynamic compilation of an existing instruction set architecture. This design approach offers the sim...Show More

Abstract:

We describe a VLIW architecture designed specifically as a target for dynamic compilation of an existing instruction set architecture. This design approach offers the simplicity and high performance of statically scheduled architectures, achieves compatibility with an established architecture, and makes use of dynamic adaptation. Thus, the original architecture is implemented using dynamic compilation, a process we refer to as DAISY (Dynamically Architected Instruction Set from Yorktown). The dynamic compiler exploits runtime profile information to optimize translations so as to extract instruction level parallelism. This paper reports different design trade-offs in the DAISY system and their impact on final system performance. The results show high degrees of instruction parallelism with reasonable translation overhead and memory usage.
Published in: IEEE Transactions on Computers ( Volume: 50, Issue: 6, June 2001)
Page(s): 529 - 548
Date of Publication: 30 June 2001

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