Design and Implementation of Three Transistor SRAM Cell using 45nm CMOS Technology

Random Access Memory plays a crucial role in data processing in various computing systems for faster applications. A processor always fetches the data from the main memory for processing, sometimes the same data may be required for the processing and need to be fetched repeatedly from the main memory results time consuming. Cache memory supports faster data storage and access by storing instances of programs and data which is routinely accessed by the processor. Therefore, the cache memory is used to store recently fetched data and when a processor requests to fetch the data the controller will first check the data in cache, if the fetched data is there in the cache then it will be fetched otherwise the controller will fetch the data from the main memory. Therefore, the cache memory is useful for improving speed of processing without wasting much time for fetching the repeated data. This paper deals with various structures of single ended S-RAM cells and proposes a novel three transistor S -RAM cell design Using Tanner 45nm Technology.