An Efficient High-Speed Lifting Based 1D/2D-DWT VLSI Architecture Using CDF-5/3 Wavelet Transform For Image Processing Applications

There are various Discrete Wavelet Transform architectures that are designed to fulfil certain requirements and criteria’s. The convolution method which is an old traditional method which requires more multipliers, hardware resources and huge memory storage which is not apt to yield high speed and efficient image processing, signal processing application designs when compared to lifting method. In this paper, we have proposed an architecture for lifting scheme based CDF-5/3 2D-DWT, which includes less mathematical computations and high speed is achieved compared to existing works. The proposed architecture design is multiplier-less and utilizes lesser number of components hence it is area efficient and also achieves high throughput rate. The RTL of this design is described in VHDL language and is synthesized in Xilinx 14.5 and target device is Virtex-5 series XC5VLX110T for testing the resulting parameters like LUTs, flip-flops and slices. Higher PSNR values and lesser MSE values are achieved when tested for different kind of images. The maximum operating frequency achieved for the designed 2D-DWT architecture is 258.358MHz. Hence the proposed 2D-DWT architecture has increased speed, less computational complexity and good hardware utilization when compared to other existing works.