Voids Reduction in Fine Pitch SiP Assembly Through Optimization of Reflow Parameters

The SiP module market has grown significantly over the past several years and is now becoming one of the fastest growing packaging technologies in the semiconductor industry owing to its lower cost, smaller form factor, higher levels of integration, and better electrical performance. The assembly of these miniature components requires advanced solder paste with finer particles size, such as Type 7 ( 2-11μm) and smaller. Increase in powder surface area as the powder size decreases might lead to formation of more void, if the flux is not capable of removing the surface oxides. Voids in solder joints are considered one of the most detrimental defects in electronic assembly as it reduces mechanical robustness of interconnection and consequently affect the reliability, especially on fine pitch devices with increasing functionality. Ideally, achieving zero void is the goal, but this is not easy to achieve. Factors, such as flux chemistry, solder paste printing, and reflow profile, have significant influences on the amount of void. While water soluble chemistry solder paste is still the mainstream in SiP modules assembly, no clean solder paste is getting increased attention. In this work, a solder paste with no clean flux chemistry will be evaluated in comparison to a water-soluble counterpart. The paper will report the printability performance of both solder pastes along with the effect of reflow parameters such as ramp-up rate, soak time, time above liquidus (TAL) and peak temperature (within the allowable process limits) towards minimizing the occurrence of voids.