A high frame rate CCD camera with region-of-interest capability

This paper presents the design and preliminary results of a custom high-speed CCD camera utilizing a Texas Instruments TC237 CCD imager chip with sub-frame window read out. The camera interfaces to a C40 digital signal processor (DSP), which is used to issue commands and read images from the camera. The camera design consists of a two-card set including the CCD imager card and the focal plane array (FPA) interface card. The CCD imager card contains the level translator and buffer circuitry for the CCD strobe lines, the TC237 CCD imager chip and a pair of analog signal processor chips, each with a 10-bit analog-to-digital converter. The analog signal processor is a TLV987 with correlated double sampling (CDS) and serial programming capability to set amplifier gain, pixel bias level and background level illumination to name a few. The second card contains a pair of field programmable gate arrays (FPGA) used to interface the CCD imager card to the C40. The goal of this camera development is to provide a high-quality, high-speed camera as part of the tracking apparatus for a free-space optical communications terminal. Preliminary data suggests frame rates of 6 kHz for 8/spl times/8 subwindows in the current testbed with 7-bit pixel resolution. Refinements in camera and testbed operation target performance goals of 17 kHz for 8/spl times/8 sub-windows with 10-bit pixel resolution.