A 25.1 dBm 25.9-dB Gain 25.4% PAE X-band Power Amplifier Utilizing Voltage Combining Transformer in 65-nm CMOS

We present an X-band two-stage power amplifier (PA) in 65-nm CMOS process using a transformer (TF)-based voltage combining technique (VTC) which achieves the highest figure of merit (FOM) among recently reported CMOS PAs. The PA architecture is constructed with two-stage push-pull amplifiers with a three-way voltage power combiner and splitter which play the main role to achieve outstanding performance. The power combining was applied in the voltage domain to increase the output device size aiming at boosting the output power of the CMOS PA. We constructed a compact two-stage PA with a push-pull structure with conjugate matchings at the input, inter-stage, and output with the capacitive neutralization technique to improve the power gain and drain efficiency. Working under a 1.2-V supply with DC quiescent current of 865-mA, the proposed PA achieved a maximum saturated output power of 25.1 dBm with a 1-dB power bandwidth of 3-GHz from 8.4-GHz to 11.4-GHz, a peak power added efficiency (PAE) of 25.4% at 10.2 GHz, a power gain of 25.9-dB at 9.5-GHz with a 3-dB gain bandwidth of 2-GHz (8.7-10.7 GHz). The total chip size is 0.9 mm
²
, and the core size excluding pads is only 0.342 mm
²
.