On-board setup-hold time measurement using FPGA based adaptive methodology

The aggressive scaling of devices and increasing density of circuits at times does not allow inbuilt circuits for testing of timing parameters, which increases the emphasis on post-silicon validation for testing of these parameters. In this paper, a versatile on-board solution for testing setup and hold time of critical paths in digital designs is proposed using FPGA. Using buffers, the proposed setup provides flexibility to maneuver the step size of the test signal's delay using coarse and fine delay for evaluating the setup/hold time, which is lucrative in testing devices with higher variations in timing parameters accurately. The adaptive nature of the design with bidirectional functionality allows robust testing of a comprehensive range of devices. The correct functioning of the system is validated by performing timing tests using Xilinx MPSoc Zynq Ultrascale FPGA.