A 50 Mbps/pin 12-input/output 40 nsec Latency Wireless Connector Using a Transmission Line Coupler with Compact SERDES IC in 180 nm CMOS

We present a prototype chip that enables 12-input/12-output wireless connector with only one transmission line coupler (TLC). The chip is capable of both the transmit mode and the receive mode operations, which can be set by an external pin. In the transmit mode, it serializes 12 input signals and drives the primary side of a TLC with an integrated 2 GHz clock signal. In the receive mode, it receives the output of the secondary side of the TLC, deserializes it and outputs 12 signals. The chip is designed and fabricated in a 180 nm CMOS process. The single supply voltage of 1.8 V is used by the chip, which draws 60 mA and 73 mA in the transmit mode and receive mode, respectively. The maximum data rate per pin is 50 Mbps, namely the total maximum data rate is 600 Mbps. Manchester code is employed so that simple clock and data recovery (CDR) circuits implemented by combinational logic circuits generate a clock signal in the receive mode. No phase locked loop-type CDR is required. Compared with the conventional one, the chip achieves 78% miniaturization, 67% power reduction and 97% latency reduction. Measurement results show that a wireless connector system using the chips is operational even when the supply voltages of the primary side and the secondary side have a mismatch of +/-11%. The wireless connector is applied to an audio system with 2 streams transferred by a single multi-bit connector. The fidelity of the sound is as good as when they are connected by 2 wires.