Maximizing Yield through Retesting of Rejected Circuits using Approximation Technique

The maximizing yield concept ensures a semi-conductor manufacturing structure towards recognizing, diminishing, and avoiding yield-related defects and contamination. According to the current scenario of technology scaling, manufacturing yield is measured in terms of the number of perfect chips produced. However, in this paper, an imperfect chip producing a good-enough result like Approximate Circuit (AxIC) can also be considered and helps enhance the yield. Hence, this paper's primary objective is to identify those acceptable circuits (AcICs) through retesting, which indirectly increases the effective yield. The basic idea is to divide the testing process into two phases. In the first phase, we follow a conventional test flow architecture and collect the rejected circuits. In the second phase, all the rejected circuits that are tested imperfect in the first phase are retested by applying the test patterns. During this phase, the circuit may produce wrong results for some test patterns, but we should ignore and continue the test until all the test patterns are applied. The test patterns for which the circuit produces a wrong result (error) are quantified and checked against the golden output for deviation. If the amount of deviation is nominal and does not affect the circuit's overall performance, then the circuit is accepted as an AxIC. Though the circuit does not precisely follow the definitions of AxICs, it can significantly contribute to the yield enhancement and termed as AcICs.