Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison With Transistor Performance

The history of integrated circuit (IC) development is another record of human challenges involving space. Efforts have been made to protect ICs from sudden malfunctions due to single-event effects (SEEs). These effects are triggered by only a single strike of particle radiation, such as an α-ray or cosmic ray, originating from our solar activity and galactic events including supernovas. This article explores how SEEs have evolved along with the progress in complementary metal-oxide-semiconductor (CMOS) digital IC technology, or device scaling, from the early micrometer-scale generations to the current nanometer-scale generations. For this purpose, focusing on basic digital elements, that is, inverters and static random access memories (SRAMs), this study collected more than 100 sets of data on four characteristic parameters of single-event upsets (SEUs) and single-event transients (SETs), both of which are undesired flips in digital logic states. The results show that all the examined parameters, such as the SEU critical charge, decrease with the device feature size. Analysis involving structure classification, such as bulk versus silicon-on-insulator (SOI) substrates and planar versus fin channels, reveals relationships between the examined SEE parameters and other device features such as the power supply voltage. All the data collected in this survey are explicitly given in tables for future exploration of IC reliability.