Normally-off computing design methodology using spintronics: from device to architectures

This work shows a promising solution to efficiently implement normally-off computing (NoC) and power analysis side-channel attack resilient designs using spin-based devices. Spintronics, as post-CMOS devices, provide interesting features such as non-volatility, which plays an essential role in NoC structures. Besides, spin-based components can naturally function as a polymorphic gate (PG) that realizes reconfigurable logic functions with inherent security attributes. However, Spintronics' utilization imposes power and area overhead compared to CMOS-based designs. Thus, herein an efficient design methodology is introduced to mitigate these overheads. This approach is first extended to realize the targeted insertion PG Modules within the VLSI implementations to make it resilient against power failure, entitled NV-Clustering. Then PARC as an extension of NV-Clustering was developed as a power-masked synthesis method in the presence of power analysis side-channel attack. PARC randomly generates power maskable building blocks with the optimum PDP and area overhead. In addition to NV-Clustering, the PARC can be expanded against fault injection approaches due to PG modules' reconfigurability to cover the faults.