Design of a Linearized Split-Load Low Power Single-Ended Ring Oscillator with High Tuning Range

In this paper, design of a power-efficient single ended ring voltage controlled oscillator (VCO) is proposed which utilizes pseudo-NMOS logic with a split-load topology to achieve an enhanced operating range. When compared with previous CMOS oscillator circuits, the proposed design demonstrates a relatively higher tuning range (from 3.93 MHz to 25.3 GHz) against a supply voltage domain of 0.3 V to 2 V (with a center frequency of 9.31 GHz). The presented architecture is simulated in 90 nm technology using the Cadence Virtuoso platform considering the effect of parasitic elements. The maximum power requirement of the structure is 0.632 mW which is low compared to reported CMOS architectures which makes the proposed circuit suitable for wide tuning ring VCO architectures required in phase locked loop (PLL) circuits of communication systems.