Robust Image Wafer Inspection

This paper presents a deep improvement of template matching technique for detecting defects in VLSI, very large-scale integration, wafer images. This method is more robust to the large device size, distortion due to image acquisition and wafer rotations. Image registration includes several steps. A golden template of the patterned wafer image under inspection can be obtained from the wafer image itself mixed to the VLSI design layout. A mapping between physical space and pixel space is needed. In addition, a more robust topology based on template matching is applied for a more accurate alignment between wafer device and template. Finally, a segmented comparison is used for finding out possible defects. A comparison between the results of the proposed method and the previous template matching technique is presented.