Performance Optimization of Semi-Custom Memory in 7nm FPGA

Designing memories which embeds multiple features involves greater challenges. Implementing additional functions to memory degrades memory performance. Applications demanding more features along with high-performance create design challenges for memories. Designing feature rich memories using complete custom approach increases design turnaround time. Generally, memory implementation in Field Programable Gate Array (FPGA) follow hybrid approach of custom and digital design techniques. Defining optimal clock-distribution network in such feature rich designs is one of the most important aspect of high-speed Silicon-on-chip (SoC) design. This paper demonstrates the custom approach by prioritizing various features in terms of criticality of timing requirements and significantly improve the clock tree performance. This approach opens new possibility for designing feature rich memory with high chances of first pass design on silicon. These kinds of memories can be seen in the FPGA's, CPU's, GPU's.