IPS-CiM: Enhancing Energy Efficiency of Intermittently-Powered Systems with Compute-in-Memory

Intermittently Powered Systems (IPS) have an ability to sustain computation progress across multiple power cycles in the presence of unreliable and sporadic harvested energy. However, with the emergence of data-intensive applications to be processed on energy-constrained IPS, it becomes challenging to handle large amounts of data with standard IPS architectures due to the von-Neumann bottleneck. To address this issue, we propose a compute-in-memory (CiM) engine which alleviates the memory-processor bottleneck and enhances energy-efficiency for transient computing workloads in IPS. We present a ferroelectric transistor (FEFET) based memory architecture which supports (a) nonvolatile memory (NVM) storage, (b) standard Boolean and arithmetic operations, (c) cyclic redundancy check for error detection and (d) edge-sensing for wireless sensory networks. Using the proposed CiM engine as a unified NVM, we construct an integrated IPS-CiM architecture based on the TI MSP430 microcontroller system with supply capacitances in the range of 10 nF -1 μF. We evaluate the proposed design with two baselines: hybrid SRAM+NVM and unified NVM architectures, both of which perform standard out-of-memory computing. We observe that for 1μF supply capacitance, IPS-CiM results in energy and performance benefits in the range of 35X-450X and 32X-400X, respectively over conventional microcontroller-based systems.