DPCLS: Improving Partial Cache Line Sparing with Dynamics for Memory Error Prevention

On modern systems, memory failures constitute around half of the total hardware failures and negatively impact system reliability, availability, and serviceability. Partial cache line sparing (PCLS) is an error-prevention mechanism in memory controllers. PCLS statically encodes the locations of the faulty nibbles of bits into a sparing directory along with the corresponding data content for replacement during memory accesses. Due to the limited number of spare entries in memory controllers, the error-prevention capability of PCLS is weak. In this paper, we propose a new approach, dynamic PCLS (DPCLS), to overcome the weakness of PCLS. Different from the static error location encoding in the sparing directory in PCLS, DPCLS exploits the temporal localities in memory errors and uses a simple policy to dynamically admit and evict the faulty nibbles spared in the directory. Empirical evaluation demonstrates that DPCLS outperforms PCLS by avoiding more errors at the same cost of snare resources.