Probe Card Lifetime Control and Abrasion Coefficient Study

With continued scaling of deep-submicron CMOS technology, more and more transistors are integrated within one die. Both the function verification and reliability performance are taken into account. In order to decrease unnecessary cost on backend package and assembling, variety of the test items and flows are transferred from FT (Final Test) level to CP (Chip Probing) level. However, the probe card is the key while wafer sort is in processing. Clean sheet, abrasion coefficient, clean frequency and overdrive impact the test stability and the cost of test directly. The balance on the above critical factors is necessary to be analyzed. The paper focuses on the abrasion coefficient model establishment and the probe card lifetime control for the specific probe card. The consumption algorithm model could be applied to improve the efficiency and control the cost of the test.