SRAM and Single Device Isolation analysis in FinFET Technology

It has been recognized that SRAM memory is an ideal vehicle for defect monitoring and yield improvement during process development because of its highly structured architecture and simplified approach to memory bitmapping . As SRAM transistors are aggressively scaled down, isolation leakage become an important reliability concern shallow trench isolation (STI) continues to scale down. This isolation leakage has to be considered to improve SRAM yield and performance. In FinFET technology, SRAM isolation is mainly dominated by NW CD and STI depth, while single device isolation is mainly impacted by AA to AA space and AA to well space. In this paper, NAA-NAA/NAA-NW/PAA-PAA/PAA-PW four types of isolation are tested to study the NW CD impact to SRAM isolation. STI depth +10 nm and STI depth +20 nm two splits are designed to research its impact to SRAM AA-well isolation. At last, AA to AA space and AA to well space influence to single device is analyzed.