Development of Low Leakage Current in Extreme PFET Device

Leakage current has become a challenge to power consumption in advanced CMOS technology. This paper reveals the low leakage of extreme PFET via Halo and LDD optimization, in 28nm high-k metal-gate (HKMG). In the same on-state current (I_ON), the drain (I_OFFD) and bulk (I_OFFB) leakage current are reduced to ~30 pA/um (~75%) and ~10 pA/um (~88%), respectively. The mechanisms of leakage reduction have been discussed in detailed. This device has great potential for IDDQ reduction via CMOS circuits design.