Low power implementation of a sigma delta decimation filter for cardiac applications

This paper reports on two main issues: low power architectures for decimation filters, and simulation tools for their RTL-level power estimation. The final aim is the design of a decimator filter for a /spl Sigma//spl Delta/ ADC, used in a pacemaker: in this field of application, the main requirement is a low power consumption, in order to preserve the batteries. First, state-of-the-art designs are presented, in order to choose the most suitable architectures for this purpose. Matlab was used to achieve the desired performances, in terms of /spl Sigma//spl Delta/ order and sampling frequency, and to find the decimation ratio. Up to now three architectures were selected and implemented (at RTL level): the classic Hogenaner's CIC (Cascade of Integrators Comb) structure and two polyphase Multi Stage Multi Rate (MSMR) structures. All the topologies were implemented in AHDL language and simulated in the CADENCE environment, to obtain a comparison in terms of the power dissipation, by adding for every block a power estimation feature. The results of these simulations are reported.