Low Power AI ASIC Design for Portable Edge Computing

For portable edge AI computing, one of the major challenges is how to achieve required computation using limited hardware resources and power consumption. An algorithm-hardware co-design process is preferred to achieve best power efficiency with reasonable high enough accuracy by using customized algorithm networks and hardware designs. Binary quantization algorithms and architecture design techniques including analog computing suitable for low power Convolutional Neural Networks applications are reviewed and compared. An augmented binary neural network is introduced, and a few guidelines are suggested for more effective low power AI ASIC design.