Interconnect Structures for Reducing Intra-Layer Metal-to-Metal Capacitances

The continuous technology scaling process has pushed the performance bottleneck from the active devices to the interconnect delay. With the more aggressive reduction in lateral dimension compared with vertical dimension, intra-layer metal-to-metal capacitances contribute significantly to the circuit delay. To address the issues, we have investigated two different technology for reducing the intra-layer capacitance. The first one is using dielectrics with structured voids to achieve low-k value. Compared with traditional porous material, the structuring of the voids gives larger porosity while maintaining the mechanical strength sufficient to withstand the CMP process. Ultimately, intra-layer metal-to-metal capacitance can be minimized by using air-gap structure. Existing air-gap technology can only cover small opening and difficult to be extensively used across a wafer. A new process utilizing an insulating 2-D material, in particular hexagonal Boron Nitride (hBN), has been developed and shown to be effective to form generic air-gap over a wide area. The physical strength over different air-gap sizes has been studied and shown to be effective over different dimensions in the micron range. The application of air-gaps for high-frequency passive components in RF ICs is discussed. A design strategy to embed air-gaps in RF components such as planar inductors is also given to improve the operating frequency and quality factor by reducing the parasitic capacitances.