Robust Clock Tree Synthesis for Near-threshold-voltage Circuits Design

Compared with clock tree working under super voltage region, near-threshold-voltage (NTV) clock tree suffers greater timing variation caused by technical parameter variation. Because clock buffers have a vital impact on clock skew and its variation under NTV, a symmetrical clock tree topology is adopted in this work to ensure better skew in nominal condition. To minimize skew variation, a buffer-library-oriented concurrent buffer insertion and sizing strategy is proposed. The buffering problem is later solved by generic algorithm in this work. Experimental result shows that σ_skewis reduced by 117% and buffer area is reduced by 72% with wire length 107% increasement overhead on average compared with reproductive results at 0.55V.