An Interface with Two-Phase Delay-Insensitive Global Communication for GALS Systems

Complex digital circuits today are implemented in UDSM (Ultra Deep-Sub-micron) MOS technology. These circuits are designed in the Systems-on-Chip (SoC) style, operating with multiple clocks due to UDSM_MOS technology. An interesting style for SoC design with multiple clocks is the GALS (Globally Asynchronous, Locally Synchronous) paradigm. As the UDSM_MOS technology causes large variations in PVT (processes, voltage, and temperature), which leads to uncertainties in wires delays, therefore, communication between locally synchronous modules is an obstacle in high-performance design, especially when it comes to long wires. In this article, we propose an interface for point-to-point GALS systems insensitive to the latency of communication wires. This robustness is achieved by communicating the encoded data in the delay-insensitive (DI) style in the LEDR (Level-encoded 2-phase Dual-Rail) code. The proposed interface uses a unique port controller to perform DI communication between locally synchronous modules, which reduces latency and area compared to other interfaces based on port controllers. A comparison with the ports controllers responsible for the communication between the four modules of four wrappers found in the literature shows that the proposed port controller leads to an average reduction in latency of 61.4% compared with the communication ports of these four wrappers.