Performance Comparison of Finite Field Multipliers for SM2 Algorithm based on FPGA Implementation

An efficient implementation of the multiplication part is one of the significant procedures of the cryptography algorithms. In this paper, the six altered parallel multiplication methods are proposed to implement in 192-bit for the SM2 algorithm. The CPAM, CSAM, Tri-Section Pezaris, Baugh-Wooley array, Modified Booth, and the Montgomery multipliers are compared by considering minimum operational speed, area, and power. We used a mod m reducer circuit for comparing with similar outputs of the multiplier architectures. Through the final comparison, the Montgomery gives the efficient result by 504 LUTs, 5.532ns timing, 0.101mW dynamic power. The proposed work is implemented on the Xilinx Virtex-7 FPGA board, and the programming language is VHDL.