Low Power Rail to Rail D Flip-Flop Using Current Mode Logic Structure

A storage element can be constructed using Current Mode Logic (CML) circuit. Folded CML D flipflop with improved switching activity circuit suffers from static power dissipation due to always ON load PMOSFETs. To reduce this static power dissipation, a positive edge triggered Low Power Rail to Rail D Flip-Flop (LPRR_DFF) using Rail to Rail D latch technique is proposed in this work. The design of Folded CML D Latch, Rail to Rail D Latch with differential buffer, Folded CML D Flip-Flop with improved switching activity and the proposed LPRR_DFF structures are implemented, simulated and analysed using gpdk45 MOSFET models of Cadence Virtuoso Spectre simulator at the power supply of 1 V at 45 nm technology. The average power, Data to Q delay (T
_DQ
), Clock to Q delay (T
_CQ
) and the transistor count of Rail to Rail D Latch with differential buffer is reduced by 99.8%,76.48%, 39.38% and 10% respectively, as compared to the Folded CML D Latch. The average power, Clock to Q delay (T
_CQ
) and the transistor count of proposed LPRR_DFF is reduced by 99.8%, 1.03% and 36.36% respectively, as compared to the Folded CML D Flip-Flop with improved switching activity.