Algorithm-Architecture Optimization for Linear and Quadratic Regression on Reconfigurable Platforms

Linear and quadratic regressions are techniques widely used in digital signal processing applications. This paper proposes a procedure and hardware architecture for the implementation of both regression methods and their mean square error (MSE) on FPGAs. Efficient computation of the bit widths of the coefficients of the regressions is carried out by finding their maxima and minima. Based on this optimization, a low-latency memory-less implementation for the computation of the MSE is proposed. Additionally, we have implemented the proposed architecture as part of a signal modulation classifier with hard real-time constraints.