Compression Molding Mechanism and Parameter Evaluation of SiP

As microelectronic market grows, the complexity and the functionality of semiconductors push the manufacture ability to evolve. On the leading edge of trend, such as high speed computing, wearable device, cloud, IoT, AiP and 5G all require a better solution for higher performance and power efficiency semiconductor packages. To meet the market demands, system in package (SiP) technology rises as having advantages of integration flexibility, smaller form factor, better electrical performance and faster time to market.Molded underfill (MUF) is highly applied process when it comes to SiP assembly process. Compression molding comes as an appealing process with more uniform flow and low mold bleed. In this paper, we developed a pre-evaluation rule to assess voids risk of compression molding process by simulation. In order to achieve our goal, we chose a bunch of different SiP type packages and performed a serious of DoEs. DoEs are decided by manipulating chosen indicators. All simulations are done with Moldex3D software.We analyzed voids and packages relation and came up with several factors which we think have significant influence on void forming. Under passive components there's solder paste, the narrow gap between two strips of solder paste is where void usually locate. We discovered that, when gap height lower than 40um and gap length larger than 1.6mm, there's high risk of void forming. On the other hand, voids also tend to between bumps under chips. Our indicator here is the area ratio of bump and chip, represent the dense level of bumps. When area ratio is large than 0.3, high risk of void forming is decided. From these conclusions we drew, a preevaluation rule is developed, meanwhile getting a closer look of void forming mechanism.